`timescale 1us/1us
module uart_byte_tx_tb_2 ();
    reg clk;
    reg[7:0] byte;
    reg reset;
    wire led;
    wire tx;
    wire ready;
    reg send_go;
    uart_byte_tx_2 uart_byte_tx_2(
        .clk(clk),
        .byte(byte),
        .reset(reset),
        .tx(tx),
        .ready(ready),
        .send_go(send_go),
        .tx_led(led)
    );
    defparam uart_byte_tx_2.contmax=10;
    initial begin
            clk<=0;
            reset<=0;
            send_go<=0;
            byte<=8'b11001100;
    #10     reset<=1;send_go<=1;
    #200    byte<=8'b10101010;
    #200    byte<=8'b01101101;send_go<=0;
    #200    byte<=8'b11100011;

    #9000   $stop;
   end

   always #1 clk<=~clk;
endmodule

